Decoupling capacitors (DECAPs) are commonly incorporated into system-on-a-chip (SoC) designs to mitigate switching noise caused by changes in current flowing through various parasitic inductances associated with the chip and a package in which the chip is located. Simultaneous switching of the input/output (I/O) and core circuits within the chip can cause a voltage droop on the power supply source by an amount approximated by ΔV=L(di/dt) where L is the effective wire inductance of the power bus (including that on the package), and di/dt is the instantaneous rate of increase of current over time. This “power supply noise” not only may increase signal delay, thereby reducing the operating frequency of the SoC, but in some cases may inadvertently cause state transitions in logic circuits within the SoC.
Some decoupling capacitors are typically placed on a circuit board upon which the SoC is placed. Such capacitors are generally effective in mitigating supply noise at relatively low frequencies. However, at higher frequencies, these capacitors are typically not as effective, so it is generally desirable to integrate on-chip decoupling capacitors into the SoC design.
In an application-specific integrated circuit (ASIC) design flow, standard-cell logic may be placed into the design using an automated design tool “place-and-route” step. After placement of the standard-cell logic, DECAPs are commonly added into the fabric of the standard-cell logic after the place-and-route step by placing the DECAPs opportunistically in area, e.g., “white space”, that is unoccupied by active logic cells. Such a “filler” methodology minimizes or eliminates any additional area overhead required for placement of these DECAP cells, which are designed to be consistent with the design rules of the CMOS technology of relevance.
In most cases, the available space for the DECAP cells after routing the functional circuit is sufficient to meet the voltage-noise requirements of the SoC design. However, in some cases, the switching activity on the chip can be very high, thus proportionately increasing the amount of on-chip decoupling capacitance needed. The capacitance requirements can be high enough that the amount of available white space on the chip is insufficient to meet the voltage noise specifications. In such cases, specialized forms of decoupling capacitors may need to be introduced.
An example of a specialized decoupling capacitor is the Metal-Insulator-Metal (“MiM”) capacitor. MiM capacitors may be formed on the chip and may provide a greater unit capacitance (μF/μm2, e.g.) than gate-oxide based capacitors. MiM capacitors have been demonstrated to offer significant advantages in enhancing the performance of high-performance circuits. Multiple types of MiM capacitors have been reported in the literature. In one example, a MiM can be formed using parallel electrodes at least partially in a metal interconnect level of the SoC. In another example, a capacitor dielectric is incorporated within a feature etched into a dielectric that is located between CMOS transistors and the first level of metallization level, e.g., metal 1. The latter example is typically used in the manufacturing of embedded dynamic RAM (DRAM). Common to both implementations is a small but non-negligible rate of defects that lead to low-resistance connection between the capacitor electrodes. Such defects can reduce device yield and/or reliability.